The present invention relates generally to the field of logic design. More specifically, the present invention is directed to a method and an apparatus for specifying address offsets and alignment for memory-mapped device.
Logic designers use hardware description language (HDL) or schematic capture to model a circuit at different level of abstractions. The circuit model is synthesized to construct a gate-level netlist.
Traditional electronic design automation tool flows require the logic designer to specify fixed addresses for each component in the system. To the extent that a component has internal addressing requirements, such as a set of contiguous registers, or address alignment requirements, the logic designer has been required to explicitly specify the addressability of each component of the device such that it meets those offset and alignment requirements. However, this requirement may be difficult for the logic designer when address relationships become complicated.
In one embodiment, a method for asserting an address alignment of an address for a memory-mapped device in a logic design is disclosed. An align primitive comprising an alignment size port, an input address port and an output address port is used. The alignment size port has data indicating a desired address boundary. The input address port is used for an address to be verified against the desired address boundary. The output address port is used to provide an address that is on the desired address boundary. The address to be verified against the desired address boundary is provided at the output address port when that address meets the desired address boundary.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description which follows.